1. Field of the Invention
The present invention generally relates to a down-converter. More specifically, the present invention relates to a down-converter using an on-chip bias circuit for enhancing symmetry and linearity of an output signal and a testing device for testing the down-converter.
2. Description of Related Art
A down-converter is a device for performing frequency translation in such a manner that the output frequencies are lower than the input frequencies. The down-converter is the last stage in an RF front end of a receiver. The down-converter affects the linearity of the RF front end of the receiver most significantly. Hence, the down-converter should be able to provide highly linear characteristics. Also, the down converter should have a 50Ω input resistor and a lower noise coefficient. In addition, considering that most low noise amplifiers have single-end output, the down-converter should also support a single-end input structure.
There is a requirement for a down-converter that implements a Class-AB single-end input, differential output double balanced mixer structure. Also, the down-converter should implement an on-chip bias loop, for improving the symmetry and linearity of the mixer. Further the down-converter on-chip implement an input impedance match circuit and an open-drain output stage. Hence, a down-converter, which by optimizing its circuit structure and each device, can achieve the objectives of a high conversion gain, high linearity, and low noise coefficient is required.